(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming surface counter-doped lightly doped drain regions in the fabrication of integrated circuits.
(2) Description of the Prior Art
Hot carrier effects resulting from high electric fields cause the most severe reliability problems in ULSI (ultra large scale integrated circuit) MOSFET devices. A lightly doped source and drain structure can effectively reduce the electric field, but this advantage is often accompanied by spacer-induced degradation. High driving current or transconductance degradation due to hot carrier damages are observed after electric stress.
Large tilt-angle implanted drain (LATID) processes have been used by a number of workers in the art to form lightly doped drains. U.S. Pat. No. 5,073,514 to Ito et al discloses the formation of an lightly doped source and drain MOSFET using LATID to form the N- and then used vertical ion implantation to form the N+ region. U.S. Pat. No. 5,147,811 to Sakagami describes the formation of a P region under the gate using LATID and then a vertical ion implant to form the N+ source/drain regions. U.S. Pat. Nos. 5,158,901 to Kosa et al and 4,771,012 to Yuba et al describe other methods of LATID.